1. Field of the Invention
Embodiments of the invention relate generally to nonvolatile memory devices. More particularly, embodiments of the invention relate to nonvolatile memory devices and related programming methods having improved performance relative to conventional nonvolatile memory devices and programming methods.
A claim of priority is made to Korean Patent Application No. 2006-22789, filed on Mar. 10, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices can be roughly divided into two categories including volatile semiconductor devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices tend to have faster read and write times than nonvolatile semiconductor memory devices. However, unlike nonvolatile semiconductor memory devices, volatile semiconductor memory devices lose stored data when disconnected from an external power source. As a result, nonvolatile semiconductor memory devices are often used to store data in electronic devices where power is limited or may be unexpectedly cut off.
There are currently many different types of nonvolatile semiconductor memory devices in existence. Examples of these devices include masked read-only memory (MROM), programmable read-only (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM), to name but a few.
Unfortunately, it has traditionally been difficult for users to update data stored in MROM, PROM, and EPROM due at least in part to difficulties in performing erase operations. However, EEPROM can be readily programmed and erased by applying appropriate voltages to individual memory cells.
One especially popular form of EEPROM is flash memory. Flash memory is popular for a wide variety of reasons, including, for example, its high degree of integration compared with other forms of EEPROM, its durability, and its performance. Among flash memories, NAND flash memory has an especially high degree of integration. Accordingly, NAND flash memory is commonly used to provide mass data storage for electronic devices.
FIG. 1 is a schematic diagram illustrating various features of a conventional NAND flash memory device. Referring to FIG. 1, the conventional NAND flash memory device comprises a memory cell array 110, a row decoder circuit 120, and a page buffer circuit 130. Within memory cell array 110, rows are driven by row decoder circuit 120, and columns are driven by page buffer circuit 130.
Memory cell array 110 comprises a plurality of memory cells divided into a plurality of memory cell blocks. For simplicity of illustration, FIG. 1 shows a single memory cell block of memory cell array 110. Other memory cell blocks in memory cell array 110 have similar functions and structures to the one illustrated. The memory cell block shown in FIG. 1 comprises a plurality of NAND strings, a plurality of word lines WL0 through WLn-1, a plurality of bit lines BL0 through BLm-1, a string select line SSL, and a ground select line GSL.
Each NAND string in the memory cell block comprises a plurality of floating gate transistors M0 through Mn-1 connected in series between a corresponding ground select transistor GST and a corresponding string select transistor SST. Each of floating gate transistors M0 through Mn-1 has a gate connected to a corresponding one of word lines WL0 through WLn-1. Each ground select transistor GST has a gate connected to ground select line GSL. Each string select transistor SST has a gate connected to string select line SSL. In addition, each string select transistor SST is connected to a corresponding bit line among bit lines BL0 through BLm-1.
Row decoder circuit 120 comprises a plurality of block select transistors BST commonly controlled by a block select control signal BS. One of block select transistors BST is connected to string select line SSL to provide a string select signal SS to string select line SSL. Another one of block select transistors BST is connected to ground select line GSL to provide a ground select signal GS to ground select line GSL. Remaining block select transistors BST are connected to respective word lines WL0 through WLn-1 to provide respective select signals SiO through Sin-1 to respective word lines WL0 through WLn-1.
Page buffer circuit 130 comprises a plurality of page buffers connected to respective bit lines BL0 through BLm-1. In some embodiments, each page buffer is connected to a pair of bit lines among bit lines BL0 through BLm-1.
In a program operation of the conventional NAND flash memory device, such as the one illustrated in FIG. 1, row decoder circuit 120 selects a word line among word lines WL0 through WLn-1 based on row address information, supplies a program word line voltage to the selected word line, and supplies a program-inhibit word line voltage to remaining word lines among word lines WL0 through WLn-1. Page buffer circuit 130 receives and stores data to be programmed into memory cell array 110 during the program operation. Page buffer circuit 130 drives each of bit lines BL0 through BLm-1 with a program bit line voltage or a program-inhibit bit line voltage depending on the data to be programmed into memory cell array 110.
In a read operation of the conventional NAND flash memory device, such as the one illustrated in FIG. 1, row decoder circuit 120 selects a word line among word lines WL0 through WLn-1 based on row address information and supplies a read word line voltage to the selected word line and a read-inhibit word line voltage to remaining word lines among word lines WL0 through WLn-1. In the read operation, page buffer circuit 130 drives each of bit lines BL0 through BLm-1 with a read bit line voltage and senses and stores data stored in memory cells connected to the selected word line through bit lines BL0 through BLm-1.
Similarly, in a verify read operation of the conventional NAND flash memory device, such as the one illustrated in FIG. 1, row decoder circuit 120 selects a word line among word lines WL0 through WLn-1 based on row address information and supplies a verify read word line voltage to the selected word line and a read-inhibit word line voltage to remaining word lines among word lines WL0 through WLn-1. In the verify read operation, page buffer circuit 130 drives each of bit lines BL0 through BLm-1 with the read bit line voltage and senses and stores data stored in memory cells connected to the selected word line through bit lines BL0 through BLm-1.
Page buffer circuit 130 detects and stores data stored in memory cells connected to the selected word line through bit lines BL0 through BLm-1.
To supply the appropriate voltages to word lines WL0 through WLn-1 during the program, read, and verify read operations, row decoder circuit 120 receives select signals Si0 to Sin-1 from a word line driver (not shown). Row decoder circuit 120 then supplies select signals Si0 through Sin-1 to respective word lines WL0 through WLn-1. Select signals Si0 through Sin-1 have voltage levels corresponding to the program word line voltage, the program-inhibit word line voltage, the read word line voltage, and the read-inhibit word line voltage, depending on which word line is selected, and which operation is being performed.
NAND flash memory is often erased and programmed using a technique commonly referred to as Fowler-Nordheim tunneling. Various methods for erasing and programming NAND flash EEPROM cells are disclosed, for example, in U.S. Pat. No. 5,473,563 entitled “NONVOLATILE SEMICONDUCTOR MEMORY”, and in U.S. Pat. No. 5,696,717 entitled “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY”.
A flash memory device may be programmed using an incremental step pulse programming (ISPP) technique to accurately control the threshold voltage distribution for memory cells in the device. One example of a conventional ISPP technique is described, for example, in U.S. Pat. No. 5,642,309 entitled “AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”.
FIG. 2 is a graph illustrating a change in a program word line voltage during a program operation for a NAND flash memory device using a conventional ISPP technique. For explanation purposes, it will be assumed that the ISPP technique of FIG. 2 is performed using the conventional NAND flash memory device illustrated in FIG. 1.
Referring to FIGS. 1 and 2, in the program operation, address data and program data are provided to the NAND flash memory device. Row decoder circuit 120 selects a word line among word lines WL0 through WLn-1 based on the address data and page buffer circuit 130 stores the program data. Typically, the program data comprises a unit of data such as a byte or a word.
The program operation comprises a sequence of program loops each comprising a program period (denoted “P” in FIG. 2) and a verify read period (denoted “V” in FIG. 2).
During the program period, page buffer circuit 130 applies the program bit line voltage and/or the program-inhibit bit line voltage to bit lines BL0 through BLm-1 based on the program data, and row decoder 120 applies the program word line voltage to the selected word line. The application of these voltages to corresponding bit and word lines tends to increase the threshold voltages of selected memory cells in the NAND flash memory device to be programmed with a logical “0”.
During the verify read period, a verify read operation is performed to detect whether the respective threshold voltages of the selected memory cells are at desired levels. In the verify read operation, page buffer circuit 130 applies the verify read bit line voltage to bit lines BL0 through BLm-1, and row decoder 120 applies the verify read word line voltage to the selected word line to sense the threshold voltage levels of the selected memory cells.
Where the threshold voltages of the selected memory cells are within desired threshold voltage distributions, the program operation is completed. Otherwise, another program loop is repeated with the program word line voltage having a level increased by an increment ΔVpgm as illustrated in FIG. 2. In the example of FIG. 2, five program loops are executed with the program word line voltage having increasing magnitudes labeled Vpgm1 through Vpgm5.
In NAND flash memories, such as the one illustrated in FIG. 1, a set of memory cells connected to the same word line are generally referred to as a “page” of memory cells. In a program operation such as that described above in relation to FIGS. 1 and 2, a page of data is generally programmed in parallel with a page of selected memory cells.
As the degree of integration in NAND flash memory device increases, the number of memory cells connected to each word line also increases. Unfortunately, as a result, the effective load capacitance for each memory cell connected to a word line may vary significantly in accordance with its location along the word line. Accordingly, the magnitude of the program word line voltages apparent at different memory cells during a program operation may vary—being attenuated at memory cells having a further distance from row decoder circuit 120. This results proves troubling since the effective load capacitance may affect the timing of the program word line voltages apparent at different memory cells.
Due to these load capacitance effects, program operations in conventional NAND flash memory devices may be limited by the timing requirements of memory cells located furthest from row decoder circuit 120. For example, the duration of each program period for a page of memory cells connected to a word line must be sufficiently long to ensure that selected memory cells located furthest from row decoder circuit 120 along the word line receive the program word line voltage for a time sufficiently long to elevate their threshold voltages by a desired amount. However, timing requirements such as these may significantly impair the overall operational performance of NAND flash memory devices.